It is solved. The stock SetSysClock()  (the one in "STM32F4xx_DSP_StdPeriph_Lib_V1.3.0\Project\STM32F4xx_StdPeriph_Templates\system_stm32f4xx.c")   is wrong...MCU get frozen within startup by that.

"Entering Over-drive mode" part of reference describes the proper sequence.

My (working!) version:

static void SetSysClock(void)  {
RCC->APB1ENR |= RCC_APB1ENR_PWREN;       // Select regulator voltage output Scale 1 mode
PWR->CR |= PWR_CR_VOS;
   
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;    // HCLK = SYSCLK / 1
RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;    // PCLK2 = HCLK / 2
RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;    // PCLK1 = HCLK / 4
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |     (RCC_PLLCFGR_PLLSRC_HSI) | (PLL_Q << 24);        // Configure the main PLL
RCC->CR |= RCC_CR_PLLON;        // Enable the main PLL

PWR->CR |= PWR_CR_ODEN;     // Enable the Over-drive to extend the clock frequency to 180 MHz
while((PWR->CSR & PWR_CSR_ODRDY) == 0)    {
        }
PWR->CR |= PWR_CR_ODSWEN;
while((PWR->CSR & PWR_CSR_ODSWRDY) == 0)    {
        }     
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;    // Configure Flash prefetch, Instruction cache, Data cache and wait state
while((RCC->CR & RCC_CR_PLLRDY) == 0)     {        // Wait till the main PLL is ready
    }
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));        // Select the main PLL as system clock source
RCC->CFGR |= RCC_CFGR_SW_PLL;
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL) {        // Wait till the main PLL is used as system clock source
    }
}