Thank you very much for this quick response! I will work on this way and keep in mind about results.

Have a nice day,

Julien.

Hello,

I have some news about my « Abort_Handler » problem. Now, this interruption also appears when I don’t use optimization.

It’s a very strange problem because Abor_Handler doesn’t occur every time. It seems that if I removed some lines in codes, sometimes, it’s sole the problem. When I had others (simple instruction that can’t produce this error), the problem comes back. It makes me crazy…. :-(

I removed all volatile variables but it doesn’t solve the problem. I haven’t inline declaration.

Could you please check my linker script files and startup file? They should be correct because I use standard files automatically generated by Ride7… My controller is a STR912W46X6.

Is it possible that this error is generated when you have a overrun stack error? How can I check that my stack doesn’t increase too much or increase it size ?

Thank you very much in advance for you useful help!

Julien.

Startup file
*********

/*
This is the default Startup for STR91x devices for the GNU toolchain

It has been designed by ST Microelectronics and modified by Raisonance.

You can use it, modify it, distribute it freely but without any waranty.

*/

.extern main

;/* the following are useful for initializing the .data section */
.extern _sidata ;/* start address for the initialization values of the .data section. defined in linker script */
.extern _sdata ;/* start address for the .data section. defined in linker script */
.extern _edata ;/* end address for the .data section. defined in linker script */

;/* the following are useful for initializing the .bss section */
.extern _sbss ;/* start address for the .bss section. defined in linker script */
.extern _ebss ;/* end address for the .bss section. defined in linker script */

/*Enable Only ONE of the following defines to select your STR91xFA Flash size*/
/*;and the Boot bank (Bank0 or Bank1).You have also to uncomment the appropriate */
/*defines in "91x_conf.h" file.*/
/*In this File/library the default size is 512Kbytes and the boot bank is Bank0*/

.set Flash_256KB_Bank0_Boot, 0
.set Flash_512KB_Bank0_Boot, 0
;.set Flash_1MB_Bank0_Boot, 0
.set Flash_1MB_Bank0_Boot, 1
.set Flash_2MB_Bank0_Boot, 0

.set Flash_256KB_Bank1_Boot, 0
.set Flash_512KB_Bank1_Boot, 0
.set Flash_2MB_Bank1_Boot, 0
.set Flash_1MB_Bank1_Boot, 0

/* Uncomment the following define when working in debug mode you have also to */
/* Uncomment the same define in "91x_conf.h" file*/

;.set debug_mode, 1
.set debug_mode, 0

/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */
.set Mode_USR, 0x10 /* User Mode */
.set Mode_FIQ, 0x11 /* FIQ Mode */
.set Mode_IRQ, 0x12 /* IRQ Mode */
.set Mode_SVC, 0x13 /* Supervisor Mode */
.set Mode_ABT, 0x17 /* Abort Mode */
.set Mode_UNDEF, 0x1B /* Undefined Mode */
.set Mode_SYS, 0x1F /* System Mode */

.equ I_Bit, 0x80 /* when I bit is set, IRQ is disabled */
.equ F_Bit, 0x40 /* when F bit is set, FIQ is disabled */

/*--- STR9X SCU specific definitions */

.set SCU_BASE_Address, 0x5C002000 /* SCU Base Address*/
.set SCU_SCR0_OFST, 0x00000034 /* System Configuration Register 0 Offset*/

/* --- STR9X FMI specific definitions*/

.set FMI_BASE_Address, 0x54000000 /* FMI Base Address*/
.set FMI_BBSR_OFST, 0x00000000 /* Boot Bank Size Register offset*/
.set FMI_NBBSR_OFST, 0x00000004 /* Non-boot Bank Size Register offset*/
.set FMI_BBADR_OFST, 0x0000000C /*Boot Bank Base Address Register offset*/
.set FMI_NBBADR_OFST, 0x00000010 /* Non-boot Bank Base Address Register offset*/
.set FMI_CR_OFST, 0x00000018 /* Control Register offset*/

.if Flash_2MB_Bank0_Boot

.set BOOT_BANK_Size, 0x6 /* Boot Bank Size Register*/
.set NON_BOOT_BANK_Size, 0x4 /* Non-boot Bank Size Register*/
.set BOOT_BANK_Address, 0x00000000 /* Boot Bank Base Address Register*/
.set NON_BOOT_BANK_Address, 0x00200000 /* Non-boot Bank Base Address Register*/

.endif

.if Flash_2MB_Bank1_Boot

.set BOOT_BANK_Size, 0x2 /* Boot Bank Size Register*/
.set NON_BOOT_BANK_Size, 0x8 /* Non-boot Bank Size Register*/
.set BOOT_BANK_Address, 0x00000000 /* Boot Bank Base Address Register*/
.set NON_BOOT_BANK_Address, 0x00200000 /* Non-boot Bank Base Address Register*/

.endif

.if Flash_1MB_Bank0_Boot

.set BOOT_BANK_Size, 0x5 /* Boot Bank Size Register*/
.set NON_BOOT_BANK_Size, 0x4 /* Non-boot Bank Size Register*/
.set BOOT_BANK_Address, 0x00000000 /* Boot Bank Base Address Register*/
.set NON_BOOT_BANK_Address, 0x00200000 /* Non-boot Bank Base Address Register*/

.endif

.if Flash_1MB_Bank1_Boot

.set BOOT_BANK_Size, 0x2 /* Boot Bank Size Register*/
.set NON_BOOT_BANK_Size, 0x7 /* Non-boot Bank Size Register*/
.set BOOT_BANK_Address, 0x00000000 /* Boot Bank Base Address Register*/
.set NON_BOOT_BANK_Address, 0x00200000 /* Non-boot Bank Base Address Register*/

.endif

.if Flash_512KB_Bank0_Boot

.set BOOT_BANK_Size, 0x4 /* Boot Bank Size Register*/
.set NON_BOOT_BANK_Size, 0x2 /* Non-boot Bank Size Register*/
.set BOOT_BANK_Address, 0x00000000 /* Boot Bank Base Address Register*/
.set NON_BOOT_BANK_Address, 0x00080000 /* Non-boot Bank Base Address Register*/

.endif

.if Flash_512KB_Bank1_Boot

.set BOOT_BANK_Size, 0x0 /* Boot Bank Size Register*/
.set NON_BOOT_BANK_Size, 0x6 /* Non-boot Bank Size Register*/
.set BOOT_BANK_Address, 0x00000000 /* Boot Bank Base Address Register*/
.set NON_BOOT_BANK_Address, 0x00080000 /* Non-boot Bank Base Address Register*/

.endif

.if Flash_256KB_Bank0_Boot

.set BOOT_BANK_Size, 0x3 /* Boot Bank Size Register*/
.set NON_BOOT_BANK_Size, 0x2 /* Non-boot Bank Size Register*/
.set BOOT_BANK_Address, 0x00000000 /* Boot Bank Base Address Register*/
.set NON_BOOT_BANK_Address, 0x00080000 /* Non-boot Bank Base Address Register*/

.endif

.if Flash_256KB_Bank1_Boot

.set BOOT_BANK_Size, 0x0 /* Boot Bank Size Register*/
.set NON_BOOT_BANK_Size, 0x5 /* Non-boot Bank Size Register*/
.set BOOT_BANK_Address, 0x00000000 /* Boot Bank Base Address Register*/
.set NON_BOOT_BANK_Address , 0x00080000 /* Non-boot Bank Base Address Register*/

.endif

***************
Sections_FLASH.ld
***************
/*
Common part of the linker scripts for STR71x devices in FLASH mode
(that is, the FLASH is seen at 0)
Copyright RAISONANCE 2005
You can use, modify and distribute thisfile freely, but without any waranty.
*/

/* Sections Definitions */

SECTIONS
{
/* for Cortex devices, the beginning of the startup code is stored in the .isr_vector section, which goes to FLASH */
.isr_vector :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} >FLASH

/* for some STRx devices, the beginning of the startup code is stored in the .flashtext section, which goes to FLASH */
.flashtext :
{
. = ALIGN(4);
*(.flashtext) /* Startup code */
. = ALIGN(4);
} >FLASH


/* the program code is stored in the .text section, which goes to Flash */
.text :
{
. = ALIGN(4);

*(.text) /* remaining code */
*(.text.*) /* remaining code */
*(.rodata) /* read-only data (constants) */
*(.rodata*)
*(.glue_7)
*(.glue_7t)

. = ALIGN(4);
_etext = .;
/* This is used by the startup in order to initialize the .data secion */
_sidata = _etext;
} >FLASH


/* for some LPC devices, there is a FLASH patch to place at a specified address */
.flashpatch :
{
. = ALIGN(4);
KEEP(*(.flashpatch)) /* flashpatch data */
. = ALIGN(4);
} >FLASHPATCH

/* for some LPC devices, there is a FLASH patch to place at a specified address
and then there is the rest of the flash */
.endflash :
{
. = ALIGN(4);
*(.endflash) /* endflash code */
. = ALIGN(4);
} >ENDFLASH

/* This is the initialized data section
The program executes knowing that the data is in the RAM
but the loader puts the initial values in the FLASH (inidata).
It is one task of the startup to copy the initial values from FLASH to RAM. */
.data : AT ( _sidata )
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_sdata = . ;

*(.data)
*(.data.*)
*(.RAMtext)

. = ALIGN(4);
/* This is used by the startup in order to initialize the .data secion */
_edata = . ;
} >RAM

/* This is the uninitialized data section */
.bss :
{
. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .;

*(.bss)
*(COMMON)

. = ALIGN(4);
/* This is used by the startup in order to initialize the .bss secion */
_ebss = . ;
} >RAM

PROVIDE ( end = _ebss );
PROVIDE ( _end = _ebss );

/* This is the user stack section
This is just to check that there is enough RAM left for the User mode stack
It should generate an error if it's full.
*/
._usrstack :
{
. = ALIGN(4);
_susrstack = . ;

. = . + _Minimum_Stack_Size ;

. = ALIGN(4);
_eusrstack = . ;
} >RAM

/* this is the FLASH Bank1 */
/* the C or assembly source must explicitly place the code or data there
using the "section" attribute */
.b1text :
{
*(.b1text) /* remaining code */
*(.b1rodata) /* read-only data (constants) */
*(.b1rodata*)
} >FLASHB1

/* this is the EXTMEM */
/* the C or assembly source must explicitly place the code or data there
using the "section" attribute */

/* EXTMEM Bank0 */
.eb0text :
{
*(.eb0text) /* remaining code */
*(.eb0rodata) /* read-only data (constants) */
*(.eb0rodata*)
} >EXTMEMB0

/* EXTMEM Bank1 */
.eb1text :
{
*(.eb1text) /* remaining code */
*(.eb1rodata) /* read-only data (constants) */
*(.eb1rodata*)
} >EXTMEMB1

/* EXTMEM Bank2 */
.eb2text :
{
*(.eb2text) /* remaining code */
*(.eb2rodata) /* read-only data (constants) */
*(.eb2rodata*)
} >EXTMEMB2

/* EXTMEM Bank0 */
.eb3text :
{
*(.eb3text) /* remaining code */
*(.eb3rodata) /* read-only data (constants) */
*(.eb3rodata*)
} >EXTMEMB3

__exidx_start = .;
__exidx_end = .;

/* after that it's only debugging information. */

/* remove the debugging information from the standard libraries */
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}

/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}

***************
STR9X_COMMON.ld
***************
/*
Common part of the linker scripts for STR91x devices
Copyright RAISONANCE 2006
You can use, modify and distribute thisfile freely, but without any waranty.
*/

/* Registers mapping */

EXTMEM_BASE = 0x30000000 ;

FMI_BASE = 0x54000000 ;
APB0_BASE = 0x58000000 ;
APB1_BASE = 0x5C000000 ;

USB_BASE = 0x70000000 ;
EMI_BASE = 0x74000000 ;
DMA_BASE = 0x78000000 ;

VIC0_BASE = 0xFFFFF000 ;
VIC1_BASE = 0xFC000000 ;

PROVIDE( _DMA = (DMA_BASE) );
PROVIDE( _EMI = (EMI_BASE) );

PROVIDE( _VIC0 = (VIC0_BASE) );
PROVIDE( VIC0VECT = (VIC0_BASE + 0x0030) );
PROVIDE( _VIC1 = (VIC1_BASE) );
PROVIDE( VIC1VECT = (VIC1_BASE + 0x0030) );

PROVIDE( _USB = (USB_BASE) );

PROVIDE( _AHBAPB0 = (APB0_BASE) );
PROVIDE( _WIU = (APB0_BASE + 0x1000) );
PROVIDE( _TIM0 = (APB0_BASE + 0x2000) );
PROVIDE( _TIM1 = (APB0_BASE + 0x3000) );
PROVIDE( _TIM2 = (APB0_BASE + 0x4000) );
PROVIDE( _TIM3 = (APB0_BASE + 0x5000) );
PROVIDE( _GPIO0 = (APB0_BASE + 0x6000) );
PROVIDE( _GPIO1 = (APB0_BASE + 0x7000) );
PROVIDE( _GPIO2 = (APB0_BASE + 0x8000) );
PROVIDE( _GPIO3 = (APB0_BASE + 0x9000) );
PROVIDE( _GPIO4 = (APB0_BASE + 0xA000) );
PROVIDE( _GPIO5 = (APB0_BASE + 0xB000) );
PROVIDE( _GPIO6 = (APB0_BASE + 0xC000) );
PROVIDE( _GPIO7 = (APB0_BASE + 0xD000) );
PROVIDE( _GPIO8 = (APB0_BASE + 0xE000) );
PROVIDE( _GPIO9 = (APB0_BASE + 0xF000) );

PROVIDE( _AHBAPB1 = (APB1_BASE) );
PROVIDE( _RTC = (APB1_BASE + 0x1000) );
PROVIDE( _SCU = (APB1_BASE + 0x2000) );
PROVIDE( _MC = (APB1_BASE + 0x3000) );
PROVIDE( _UART0 = (APB1_BASE + 0x4000) );
PROVIDE( _UART1 = (APB1_BASE + 0x5000) );
PROVIDE( _UART2 = (APB1_BASE + 0x6000) );
PROVIDE( _SPI0 = (APB1_BASE + 0x7000) );
PROVIDE( _SPI1 = (APB1_BASE + 0x8000) );
PROVIDE( _CAN = (APB1_BASE + 0x9000) );
PROVIDE( _ADC = (APB1_BASE + 0xA000) );
PROVIDE( _WDG = (APB1_BASE + 0xB000) );
PROVIDE( _I2C0 = (APB1_BASE + 0xC000) );
PROVIDE( _I2C1 = (APB1_BASE + 0xD000) );

/* default stack sizes.

These are used by the startup in order to allocate stacks for the different modes.
*/

__SVC_Stack_Size = 256 ;
__IRQ_Stack_Size = 1024 ;
__USR_Stack_Size = 1024 ;
__FIQ_Stack_Size = 256 ;
__ABT_Stack_Size = 256 ;
__UND_Stack_Size = 256 ;

__SVC_Stack_Init = _estack ;
__IRQ_Stack_Init = __SVC_Stack_Init - __SVC_Stack_Size ;
__USR_Stack_Init = __IRQ_Stack_Init - __IRQ_Stack_Size ;
__FIQ_Stack_Init = __USR_Stack_Init - __USR_Stack_Size ;
__ABT_Stack_Init = __FIQ_Stack_Init - __FIQ_Stack_Size ;
__UND_Stack_Init = __ABT_Stack_Init - __ABT_Stack_Size ;

/*"PROVIDE" allows to easily override these values from an object file or the commmand line.*/
PROVIDE ( _SVC_Stack_Init = __SVC_Stack_Init ) ;
PROVIDE ( _IRQ_Stack_Init = __IRQ_Stack_Init ) ;
PROVIDE ( _USR_Stack_Init = __USR_Stack_Init ) ;
PROVIDE ( _FIQ_Stack_Init = __FIQ_Stack_Init ) ;
PROVIDE ( _ABT_Stack_Init = __ABT_Stack_Init ) ;
PROVIDE ( _UND_Stack_Init = __UND_Stack_Init ) ;

/*
the user mode stack is an exception because we want it at the end of the RAM.
therefore, we just check against a minimum.
The value below is the minimum memory required for ALL THE STACKS.
There will be a link error if there is not this amount of RAM free at the end.
*/
_Minimum_Stack_Size = 0xC00 ;

/* default ISR addresses.

The startup needs these addresses defined from another object file.
In case they are not, these PROVIDEs redirect them to the Reset.

_start must be defined, usually in the startup.
*/

PROVIDE( Undefined_Handler = _start );
PROVIDE( SWI_Handler = _start );
PROVIDE( Prefetch_Handler = _start );
PROVIDE( Abort_Handler = _start );
PROVIDE( FIQ_Handler = _start );
PROVIDE( T0TIMI_IRQHandler = _start );
PROVIDE( FLASH_IRQHandler = _start );
PROVIDE( RCCU_IRQHandler = _start );
PROVIDE( RTC_IRQHandler = _start );
PROVIDE( WDG_IRQHandler = _start );
PROVIDE( XTI_IRQHandler = _start );
PROVIDE( USBHP_IRQHandler = _start );
PROVIDE( I2C0ITERR_IRQHandler = _start );
PROVIDE( I2C1ITERR_IRQHandler = _start );
PROVIDE( UART0_IRQHandler = _start );
PROVIDE( UART1_IRQHandler = _start );
PROVIDE( UART2_IRQHandler = _start );
PROVIDE( UART3_IRQHandler = _start );
PROVIDE( BSPI0_IRQHandler = _start );
PROVIDE( BSPI1_IRQHandler = _start );
PROVIDE( I2C0_IRQHandler = _start );
PROVIDE( I2C1_IRQHandler = _start );
PROVIDE( CAN_IRQHandler = _start );
PROVIDE( ADC12_IRQHandler = _start );
PROVIDE( T1TIMI_IRQHandler = _start );
PROVIDE( T2TIMI_IRQHandler = _start );
PROVIDE( T3TIMI_IRQHandler = _start );
PROVIDE( HDLC_IRQHandler = _start );
PROVIDE( USBLP_IRQHandler = _start );
PROVIDE( T0TOI_IRQHandler = _start );
PROVIDE( T0OC1_IRQHandler = _start );
PROVIDE( T0OC2_IRQHandler = _start );

Strange...

For my application, I have used startup file that I found in ST library repository.

I tried with startup file that I found (this morning) in source file of Raisonnance “crt0_STR91x.s” and now I haven’t “Abort_Handler interrupt”. I can also use optimization without to have Abort_Handler interrupt. Really strange!

I have compared them but I don’t know much about startup file. Does someone could check if differences that could cause Abort_Handler? It should be really interesting to know what produce this error…

I will continue to work like that and I hope that the problem will never appears. I keep you in mind about that.

Thanks,

Julien.

**************
Startup from ST
**************

/*
This is the default Startup for STR91x devices for the GNU toolchain

It has been designed by ST Microelectronics and modified by Raisonance.

You can use it, modify it, distribute it freely but without any waranty.

*/

.extern main

;/* the following are useful for initializing the .data section */
.extern _sidata ;/* start address for the initialization values of the .data section. defined in linker script */
.extern _sdata ;/* start address for the .data section. defined in linker script */
.extern _edata ;/* end address for the .data section. defined in linker script */

;/* the following are useful for initializing the .bss section */
.extern _sbss ;/* start address for the .bss section. defined in linker script */
.extern _ebss ;/* end address for the .bss section. defined in linker script */

/*Enable Only ONE of the following defines to select your STR91xFA Flash size*/
/*;and the Boot bank (Bank0 or Bank1).You have also to uncomment the appropriate */
/*defines in "91x_conf.h" file.*/
/*In this File/library the default size is 512Kbytes and the boot bank is Bank0*/

.set Flash_256KB_Bank0_Boot, 0
.set Flash_512KB_Bank0_Boot, 0
;.set Flash_1MB_Bank0_Boot, 0
.set Flash_1MB_Bank0_Boot, 1
.set Flash_2MB_Bank0_Boot, 0

.set Flash_256KB_Bank1_Boot, 0
.set Flash_512KB_Bank1_Boot, 0
.set Flash_2MB_Bank1_Boot, 0
.set Flash_1MB_Bank1_Boot, 0

/* Uncomment the following define when working in debug mode you have also to */
/* Uncomment the same define in "91x_conf.h" file*/

.set debug_mode, 1
;.set debug_mode, 0

/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */
.set Mode_USR, 0x10 /* User Mode */
.set Mode_FIQ, 0x11 /* FIQ Mode */
.set Mode_IRQ, 0x12 /* IRQ Mode */
.set Mode_SVC, 0x13 /* Supervisor Mode */
.set Mode_ABT, 0x17 /* Abort Mode */
.set Mode_UNDEF, 0x1B /* Undefined Mode */
.set Mode_SYS, 0x1F /* System Mode */

.equ I_Bit, 0x80 /* when I bit is set, IRQ is disabled */
.equ F_Bit, 0x40 /* when F bit is set, FIQ is disabled */

/*--- STR9X SCU specific definitions */

.set SCU_BASE_Address, 0x5C002000 /* SCU Base Address*/
.set SCU_SCR0_OFST, 0x00000034 /* System Configuration Register 0 Offset*/

/* --- STR9X FMI specific definitions*/

.set FMI_BASE_Address, 0x54000000 /* FMI Base Address*/
.set FMI_BBSR_OFST, 0x00000000 /* Boot Bank Size Register offset*/
.set FMI_NBBSR_OFST, 0x00000004 /* Non-boot Bank Size Register offset*/
.set FMI_BBADR_OFST, 0x0000000C /*Boot Bank Base Address Register offset*/
.set FMI_NBBADR_OFST, 0x00000010 /* Non-boot Bank Base Address Register offset*/
.set FMI_CR_OFST, 0x00000018 /* Control Register offset*/

.if Flash_2MB_Bank0_Boot

.set BOOT_BANK_Size, 0x6 /* Boot Bank Size Register*/
.set NON_BOOT_BANK_Size, 0x4 /* Non-boot Bank Size Register*/
.set BOOT_BANK_Address, 0x00000000 /* Boot Bank Base Address Register*/
.set NON_BOOT_BANK_Address, 0x00200000 /* Non-boot Bank Base Address Register*/

.endif

.if Flash_2MB_Bank1_Boot

.set BOOT_BANK_Size, 0x2 /* Boot Bank Size Register*/
.set NON_BOOT_BANK_Size, 0x8 /* Non-boot Bank Size Register*/
.set BOOT_BANK_Address, 0x00000000 /* Boot Bank Base Address Register*/
.set NON_BOOT_BANK_Address, 0x00200000 /* Non-boot Bank Base Address Register*/

.endif

.if Flash_1MB_Bank0_Boot

.set BOOT_BANK_Size, 0x5 /* Boot Bank Size Register*/
.set NON_BOOT_BANK_Size, 0x4 /* Non-boot Bank Size Register*/
.set BOOT_BANK_Address, 0x00000000 /* Boot Bank Base Address Register*/
.set NON_BOOT_BANK_Address, 0x00200000 /* Non-boot Bank Base Address Register*/

.endif

.if Flash_1MB_Bank1_Boot

.set BOOT_BANK_Size, 0x2 /* Boot Bank Size Register*/
.set NON_BOOT_BANK_Size, 0x7 /* Non-boot Bank Size Register*/
.set BOOT_BANK_Address, 0x00000000 /* Boot Bank Base Address Register*/
.set NON_BOOT_BANK_Address, 0x00200000 /* Non-boot Bank Base Address Register*/

.endif

.if Flash_512KB_Bank0_Boot

.set BOOT_BANK_Size, 0x4 /* Boot Bank Size Register*/
.set NON_BOOT_BANK_Size, 0x2 /* Non-boot Bank Size Register*/
.set BOOT_BANK_Address, 0x00000000 /* Boot Bank Base Address Register*/
.set NON_BOOT_BANK_Address, 0x00080000 /* Non-boot Bank Base Address Register*/

.endif

.if Flash_512KB_Bank1_Boot

.set BOOT_BANK_Size, 0x0 /* Boot Bank Size Register*/
.set NON_BOOT_BANK_Size, 0x6 /* Non-boot Bank Size Register*/
.set BOOT_BANK_Address, 0x00000000 /* Boot Bank Base Address Register*/
.set NON_BOOT_BANK_Address, 0x00080000 /* Non-boot Bank Base Address Register*/

.endif

.if Flash_256KB_Bank0_Boot

.set BOOT_BANK_Size, 0x3 /* Boot Bank Size Register*/
.set NON_BOOT_BANK_Size, 0x2 /* Non-boot Bank Size Register*/
.set BOOT_BANK_Address, 0x00000000 /* Boot Bank Base Address Register*/
.set NON_BOOT_BANK_Address, 0x00080000 /* Non-boot Bank Base Address Register*/

.endif

.if Flash_256KB_Bank1_Boot

.set BOOT_BANK_Size, 0x0 /* Boot Bank Size Register*/
.set NON_BOOT_BANK_Size, 0x5 /* Non-boot Bank Size Register*/
.set BOOT_BANK_Address, 0x00000000 /* Boot Bank Base Address Register*/
.set NON_BOOT_BANK_Address , 0x00080000 /* Non-boot Bank Base Address Register*/

.endif

/*; --- System memory locations */

/* init value for the stack pointer. defined in linker script */
.extern _estack

;/* Stack Sizes. The default values are in the linker script, but they can be overriden. */
.extern _UND_Stack_Init
.extern _SVC_Stack_Init
.extern _ABT_Stack_Init
.extern _FIQ_Stack_Init
.extern _IRQ_Stack_Init
.extern _USR_Stack_Init

.extern _UND_Stack_Size
.extern _SVC_Stack_Size
.extern _ABT_Stack_Size
.extern _FIQ_Stack_Size
.extern _IRQ_Stack_Size
.extern _USR_Stack_Size

SVC_Stack = _SVC_Stack_Init /*_estack*/ /*; 256 byte SVC stack at*/
/*; top of memory */

IRQ_Stack = _IRQ_Stack_Init /*SVC_Stack - 256*/ /*; followed by IRQ stack */
USR_Stack = _USR_Stack_Init /*IRQ_Stack-1024*/ /*; followed by USR stack */
FIQ_Stack = _FIQ_Stack_Init /*USR_Stack-1024*/ /*; followed by FIQ stack*/
ABT_Stack = _ABT_Stack_Init /*FIQ_Stack-256*/ /*; followed by ABT stack */
UNDEF_Stack = _UND_Stack_Init /*ABT_Stack-256*/ /*; followed by UNDEF stack */

.equ VectorAddress, 0xFFFFF030 /* VIC Vector address register address.*/

.globl start
.globl _start
.globl _startup
.section .flashtext,"ax",%progbits
start:
_start:
_startup:

ldr PC, =Reset_Handler
ldr PC, =UndefinedHandler
ldr PC, =SWIHandler
ldr PC, =PrefetchAbortHandler
ldr PC, =DataAbortHandler
nop /*; Reserved vector*/
ldr PC, =IRQHandler

/********************************************************************************
* Function Name : FIQHandler
* Description : This function is called when FIQ exception is entered.
* Input : none
* Output : none
********************************************************************************/
FIQHandler:
SUB lr,lr,#4 /* Update the link register.*/
STMFD sp!,{r0-r4,lr} /* Save The workspace plus the current return*/
/* address lr_fiq into the FIQ stack.*/
BL FIQ_Handler /*; Branch to FIQ_Handler.*/

LDMFD sp!,{r0-r4,pc}^ /*Return to the instruction following...*/
/* ...the exception interrupt.*/

.text

/*;*******************************************************************************
;* Macro Name : SaveContext
;* Description : This macro used to save the context before entering
; an exception handler.
;* Input : The range of registers to store.
;* Output : none
;*******************************************************************************/

.macro Savecontext $r0,$r4
STMFD sp!,{r0-r4,lr} /* Save The workspace plus the current return*/
/* address lr_ mode into the stack.*/
.endm
/*;*******************************************************************************
;* Macro Name : RestoreContext
;* Description : This macro used to restore the context to return from
; an exception handler and continue the program execution.
;* Input : The range of registers to restore.
;* Output : none
;*******************************************************************************/
.macro RestoreContext $r0,$r4

LDMFD sp!,{r0-r4,pc}^ /* Return to the instruction following...*/
/*...the exception interrupt.*/

.endm

/*;*******************************************************************************
;* Function Name : UndefinedHandler
;* Description : This function called when undefined instruction
; exception is entered.
;* Input : none
;* Output : none
;*******************************************************************************/

UndefinedHandler:
SaveContext r0,r4 /*; Save the workspace plus the current*/
BL Undefined_Handler /*; Branch to Undefined_Handler.*/
RestoreContext r0,r4 /*; Return to the instruction following..*/
/*; ...the undefined instruction.*/

/*;*******************************************************************************
;* Function Name : SWIHandler
;* Description : This function called when SWI instruction executed.
;* Input : none
;* Output : none
;*******************************************************************************/

SWIHandler:
SaveContext r0,r4 /*; Save the workspace plus the current*/
/*; return address lr_ svc and spsr_svc.*/
BL SWI_Handler /*; Branch to SWI_Handler.*/
RestoreContext r0,r4 /*; Return to the instruction following...*/
/*; ...the SWI instruction.*/

/*;*******************************************************************************
;* Function Name : PrefetchAbortHandler
;* Description : This function called when Prefetch Abort
; exception is entered.
;* Input : none
;* Output : none
;*******************************************************************************/

PrefetchAbortHandler:
SUB lr,lr,#4 /* ; Update the link register.*/
SaveContext r0,r4 /*; Save the workspace plus the current*/
/*; return address lr_abt and spsr_abt.*/
BL Prefetch_Handler /*; Branch to Prefetch_Handler. */
RestoreContext r0,r4 /*; Return to the instruction following that... */
/*; ...has generated the prefetch abort exception.*/

/*;*******************************************************************************
;* Function Name : DataAbortHandler
;* Description : This function is called when Data Abort
; exception is entered.
;* Input : none
;* Output : none
;********************************************************************************/

DataAbortHandler:
SUB lr,lr,#8 /*; Update the link register.*/
SaveContext r0,r4 /*; Save the workspace plus the current*/
/*; return address lr_ abt and spsr_abt.*/
BL Abort_Handler /*; Branch to Abort_Handler.*/
RestoreContext r0,r4 /*; Return to the instruction following that...*/
/*; ...has generated the data abort exception.*/

/********************************************************************************
* Function Name : IRQHandler
* Description : This function is called when IRQ exception is entered.
* Input : none
* Output : none
********************************************************************************/

IRQHandler:
SUB lr,lr ,#4
SaveContext r0,r4
LDR r0, = VectorAddress
LDR r0, [r0] /* Read the routine address from VIC0 Vector Address register */

BLX r0 /* Branch with link to the IRQ handler. */
RestoreContext r0,r4

/***********************************************************************************************/
Reset_Handler:
ldr PC, =NextInst

NextInst:
/* ------------------------------------------------------------------------------
Description : This delay is added to let JTAG debuggers able to connect
to STR91x micro then load the program even if a previously
flash code is halting the CPU core. This may happen when the
flash content is corrupt by containing a "bad" code like entering
soon to IDLE or SLEEP Low power modes.
When going to production/Release code and to remove this Start-up
delay, Please comment the "Debug_mode" define above.
--------------------------------------------------------------------------------*/

.if debug_mode

MOV r0, #0x4000
Loop:
SUBS r0,r0, #1
SUBS r0,r0, #1
SUBS r0,r0, #1
SUBS r0,r0, #1
SUBS r0,r0, #1
SUBS r0,r0, #1
SUBS r0,r0, #1
SUBS r0,r0, #1
BNE Loop
.endif

/* ------------------------------------------------------------------------------
Description : Enable the Buffered mode.
To use buffered mode access you have to uncomment Buffered
define on the 91x_conf.h file
------------------------------------------------------------------------------*/

MRC p15, 0, r0, c1, c0, 0 /* Read CP15 register 1 into r0*/
ORR r0, r0, #0x8 /* Enable Write Buffer on AHB*/
MCR p15, 0, r0, c1, c0, 0 /* Write CP15 register 1 */
/*------------------------------------------------------------------------------
Description : Write Buffer in ITCM may cause the Flash “write then read”
command order reversed and cause flash error.
To maintain the right order, bit 18 (Instruction TCM order bit)
in the Configuration Registers of the ARM966E-S core must be set.
------------------------------------------------------------------------------*/

MOV r0, #0x40000
MCR p15,0x1,r0,c15,c1,0

/*------------------------------------------------------------------------------
Description : FMI Registers configuration depending on the Flash size selected,
and the boot bank.

After reset, the application program has to write the size and start
address of Bank 1 in the FMI_BBSR and FMI_BBADR registers and the size and
start address of Bank 0 in the FMI_NBBSR and FMI_NBBADR registers.
------------------------------------------------------------------------------*/

LDR R6, =FMI_BASE_Address
LDR R7, = BOOT_BANK_Size /* BOOT BANK Size=*/
STR R7, [R6, #FMI_BBSR_OFST] /* (2^BOOT_BANK_Size) * 32KBytes */
LDR R7, = NON_BOOT_BANK_Size /* NON BOOT BANK Size =*/
STR R7, [R6, #FMI_NBBSR_OFST] /* (2^NON_BOOT_BANK_Size) * 8KBytes*/
LDR R7, =BOOT_BANK_Address /* BOOT BANK Address*/
MOV R7, R7 ,LSR #0x2
STR R7, [R6, #FMI_BBADR_OFST]
LDR R7, =NON_BOOT_BANK_Address /* BOOT BANK Address*/
MOV R7, R7 ,LSR #0x2
STR R7, [R6, #FMI_NBBADR_OFST]


LDR R7, = 0x19 /* Enable Both banks*/
STR R7, [R6, #FMI_CR_OFST]


/* --- Enable 96K of RAM & Disable DTCM & AHB wait-states*/

LDR R0, = SCU_BASE_Address
LDR R1, = 0x0191
STR R1, [R0, #SCU_SCR0_OFST]

/*; Initialize Stack pointer for various CPU Modes.*/


msr CPSR_c, #Mode_FIQ|I_Bit|F_Bit /* No interrupts */
ldr SP, =FIQ_Stack

msr CPSR_c, #Mode_IRQ|I_Bit|F_Bit /* No interrupts */
ldr SP, =IRQ_Stack

MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit /* No interrupts */
LDR SP, =ABT_Stack

MSR CPSR_c, #Mode_UNDEF|I_Bit|F_Bit /* No interrupts */
LDR SP, =UNDEF_Stack

MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit /* No interrupts */
LDR SP, =_estack /*RAM_Limit*/


/* --- Now change to USR/SYS mode and set up User mode stack, */
MSR CPSR_c, #Mode_SYS /* IRQs & FIQs are now enable*/
ldr SP, =USR_Stack

/* copy the initial values for .data section from FLASH to RAM */
ldr R1, =_sidata
ldr R2, =_sdata
ldr R3, =_edata
_reset_inidata_loop:
cmp R2, R3
ldrlO R0, [R1], #4
strlO R0, [R2], #4
blO _reset_inidata_loop

/* Clear the .bss section */
mov r0,#0 /* get a zero */
ldr r1,=_sbss /* point to bss start */
ldr r2,=_ebss /* point to bss end */
_reset_inibss_loop:
cmp r1,r2 /* check if some data remains to clear */
strlo r0,[r1],#4 /* clear 4 bytes */
blo _reset_inibss_loop /* loop until done */

/************************************************************************************************/

/*; --- Now enter the C code */
ldr PC, =main


/*
END
/**************
****** (C) COPYRIGHT 2008 STMicroelectronics *****
****** (C) COPYRIGHT 2008 RAISONANCE *****

END OF FILE****/

***************
Startup from RIDE7
***************
/*
This is the default Startup for STR91x devices for the GNU toolchain

It has been designed by ST Microelectronics and modified by Raisonance.

You can use it, modify it, distribute it freely but without any waranty.

*/

.extern main

;/* the following are useful for initializing the .data section */
.extern _sidata ;/* start address for the initialization values of the .data section. defined in linker script */
.extern _sdata ;/* start address for the .data section. defined in linker script */
.extern _edata ;/* end address for the .data section. defined in linker script */

;/* the following are useful for initializing the .bss section */
.extern _sbss ;/* start address for the .bss section. defined in linker script */
.extern _ebss ;/* end address for the .bss section. defined in linker script */

;/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */
.set Mode_USR, 0x10 ;/* User Mode */
.set Mode_FIQ, 0x11 ;/* FIQ Mode */
.set Mode_IRQ, 0x12 ;/* IRQ Mode */
.set Mode_SVC, 0x13 ;/* Supervisor Mode */
.set Mode_ABT, 0x17 ;/* Abort Mode */
.set Mode_UNDEF, 0x1B ;/* Undefined Mode */
.set Mode_SYS, 0x1F ;/* System Mode */

.extern VIC0VECT
.extern VIC1VECT

.equ I_Bit, 0x80 ;/* when I bit is set, IRQ is disabled */
.equ F_Bit, 0x40 ;/* when F bit is set, FIQ is disabled */

/*; --- System memory locations */

;/* init value for the stack pointer. defined in linker script */
.extern _estack

;/* Stack Sizes. The default values are in the linker script, but they can be overriden. */
.extern _UND_Stack_Init
.extern _SVC_Stack_Init
.extern _ABT_Stack_Init
.extern _FIQ_Stack_Init
.extern _IRQ_Stack_Init
.extern _USR_Stack_Init

.extern _UND_Stack_Size
.extern _SVC_Stack_Size
.extern _ABT_Stack_Size
.extern _FIQ_Stack_Size
.extern _IRQ_Stack_Size
.extern _USR_Stack_Size

SVC_Stack = _SVC_Stack_Init /*_estack*/ /*; 256 byte SVC stack at*/
/*; top of memory */

IRQ_Stack = _IRQ_Stack_Init /*SVC_Stack - 256*/ /*; followed by IRQ stack */
USR_Stack = _USR_Stack_Init /*IRQ_Stack-1024*/ /*; followed by USR stack */
FIQ_Stack = _FIQ_Stack_Init /*USR_Stack-1024*/ /*; followed by FIQ stack*/
ABT_Stack = _ABT_Stack_Init /*FIQ_Stack-256*/ /*; followed by ABT stack */
UNDEF_Stack = _UND_Stack_Init /*ABT_Stack-256*/ /*; followed by UNDEF stack */

/*; STR9X register specific definition*/

.equ SCRO_AHB_UNB, 0x5C002034

/***************************************************************************************/

/*;*******************************************************************************
;* Macro Name : SaveContext
;* Description : This macro used to save the context before entering
; an exception handler.
;* Input : The range of registers to store.
;* Output : none
;*******************************************************************************/

.macro Savecontext $r0,$r12
STMFD sp!,{r0-r12,lr}
MRS r1,spsr
STMFD sp!,{r1}
.endm
/*;*******************************************************************************
;* Macro Name : RestoreContext
;* Description : This macro used to restore the context to return from
; an exception handler and continue the program execution.
;* Input : The range of registers to restore.
;* Output : none
;*******************************************************************************/
.macro RestoreContext $r0,$r12
LDMFD sp!,{r1} /*; Restore the saved spsr_mode into r1.*/
MSR spsr_cxsf,r1 /*; Restore spsr_mode.*/
LDMFD sp!,{r0-r12,pc}^ /*; Return to the instruction following...*/
.endm /*; ...the exception interrupt.*/

.globl start
.globl _start
.globl _startup

.section .flashtext,"ax",%progbits
start:
_start:
_startup:

ldr PC, =Reset_Handler
ldr PC, =UndefinedHandler
ldr PC, =SWIHandler
ldr PC, =PrefetchAbortHandler
ldr PC, =DataAbortHandler
nop /*; Reserved vector*/
ldr PC, =IRQHandler
ldr PC, =FIQHandler

.text

/*;*******************************************************************************
;* Function Name : FIQHandler
;* Description : This function is called when FIQ
; exception is entered.
;* Input : none
;* Output : none
;******************************************************************************* */

FIQHandler:
SUB lr,lr,#4 /*; Update the link register.*/
SaveContext r0,r7 /* ; Save the workspace plus the current*/
/*; return address lr_ fiq and spsr_fiq.*/
ldr PC,=FIQ_Handler /*; Branch to FIQ_Handler.*/
RestoreContext r0,r7 /*; Restore the context and return to the...*/
/*; ...program execution.*/

/*;*******************************************************************************
;* Function Name : UndefinedHandler
;* Description : This function called when undefined instruction
; exception is entered.
;* Input : none
;* Output : none
;*******************************************************************************/

UndefinedHandler:
SaveContext r0,r12 /*; Save the workspace plus the current*/
ldr PC,=Undefined_Handler /*; Branch to Undefined_Handler.*/
RestoreContext r0,r12 /*; Return to the instruction following..*/
/*; ...the undefined instruction.*/

/*;*******************************************************************************
;* Function Name : SWIHandler
;* Description : This function called when SWI instruction executed.
;* Input : none
;* Output : none
;*******************************************************************************/

SWIHandler:
SaveContext r0,r12 /*; Save the workspace plus the current*/
/*; return address lr_ svc and spsr_svc.*/
ldr PC,=SWI_Handler /*; Branch to SWI_Handler.*/
RestoreContext r0,r12 /*; Return to the instruction following...*/
/*; ...the SWI instruction.*/

/*;*******************************************************************************
;* Function Name : IRQHandler
;* Description : This function called when IRQ exception is entered.
;* Input : none
;* Output : none
;*******************************************************************************/

IRQHandler:
SUB lr,lr,#4 /*Update the link register*/
SaveContext r0,r12 /*Save the workspace plus the current*/
/*return address lr_irq and spsr_irq*/
LDR r0, = VIC0VECT
LDR r0, [r0] /*Read the routine address*/
LDR r1, = VIC1VECT
LDR r1, [r1]
/*Padding between the acknowledge and re-enable of interrupts*/
/*For more details, please refer to the following URL*/
/*http://www.arm.com/support/faqip/3682.html*/
NOP
NOP
MSR cpsr_c,#0x1F /*Switch to SYS mode and enable IRQ*/
STMFD sp!,{lr} /*Save the link register.*/
LDR lr, = IRQ_ReturnAddress /*Read the return address.*/
BX r0 /*MOV pc, r0*/ /*Branch to the IRQ handler.*/
IRQ_ReturnAddress:
LDMFD sp!,{lr} /*Restore the link register.*/
MSR cpsr_c,#0xD2 | I_Bit /*Switch to IRQ mode and disable IRQ*/
LDR r0, = VIC0VECT /*Write to the VectorAddress to clear the*/
STR r0, [r0] /*respective interrupt in the internal interrupt*/
LDR r1, = VIC1VECT /*Write to the VectorAddressDaisy to clear the*/
STR r1,[r1] /*respective interrupt in the internal interrupt*/
RestoreContext r0,r12 /*Restore the context and return to the...*/
/*...program execution.*/


/*;*******************************************************************************
;* Function Name : PrefetchAbortHandler
;* Description : This function called when Prefetch Abort
; exception is entered.
;* Input : none
;* Output : none
;*******************************************************************************/

PrefetchAbortHandler:
SUB lr,lr,#4 /* ; Update the link register.*/
SaveContext r0,r12 /*; Save the workspace plus the current*/
/*; return address lr_abt and spsr_abt.*/
ldr PC,=Prefetch_Handler /*; Branch to Prefetch_Handler. */
RestoreContext r0,r12 /*; Return to the instruction following that... */
/*; ...has generated the prefetch abort exception.*/

/*;*******************************************************************************
;* Function Name : DataAbortHandler
;* Description : This function is called when Data Abort
; exception is entered.
;* Input : none
;* Output : none
;********************************************************************************/

DataAbortHandler:
SUB lr,lr,#8 /*; Update the link register.*/
SaveContext r0,r12 /*; Save the workspace plus the current*/
/*; return address lr_ abt and spsr_abt.*/
ldr PC,=Abort_Handler /*; Branch to Abort_Handler.*/
RestoreContext r0,r12 /*; Return to the instruction following that...*/
/*; ...has generated the data abort exception.*/

/*;*******************************************************************************
;* Macro Name : IRQ_to_SYS
;* Description : This macro used to switch form IRQ mode to SYS mode
;* Input : none.
;* Output : none
;*******************************************************************************/
.macro IRQ_to_SYS
MSR cpsr_c,#0x1F
STMFD sp!,{lr}
.endm
/*;*******************************************************************************
;* Macro Name : SYS_to_IRQ
;* Description : This macro used to switch from SYS mode to IRQ mode
; then to return to IRQHnadler routine.
;* Input : none.
;* Output : none.
;*******************************************************************************/
.macro SYS_to_IRQ
LDMFD sp!,{lr} /*; Restore the link register. */
MSR cpsr_c,#0xD2 /*; Switch to IRQ mode.*/
MOV pc,lr /*; Return to IRQHandler routine to clear the*/
/*; pending bit.*/
.endm

/***********************************************************************************************/
Reset_Handler:
ldr PC, =NextInst

NextInst:

nop
nop
nop
nop
nop
nop
nop
nop
nop

/*; --- ARM9 core configuration*/

/* configure flash */
ldr R0, =0x54000000
ldr R7, =_bb_size /*boot bank size configuration 0x4 */
str R7, [R0]

ldr R0, =0x54000004
ldr R1, =_nbb_size /*non-boot bank size configuration 0x3 */
str R1, [R0]

/*
don't change the boot bank address because this code is probably executing from it.
and it is happy staying at address zero anyways.
*/
/*ldr R0, =0x5400000C*/
/*ldr R1, =0x0*/ /*boot bank address configuration */
/*str R1, [R0]*/

ldr R0, =0x54000010
ldr R1, =_nbb_addr /*non-boot bank address configuration 0x20000 */
str R1, [R0]

ldr R0, =0x54000018
ldr R1, =0x18 /*enable both banks*/
str R1, [R0]

/* configure ram */
Enable_SRAM_96K:
ldr R0, =SCRO_AHB_UNB
ldr R1, =0x0196 /*TODO: the value written there should depend on the derivative...*/
str R1, [R0]

MRC P15, 0, r0, c1, c0, 0

/*; Initialize Stack pointer for various CPU Modes.*/
MSR CPSR_c, #Mode_ABT|F_Bit|I_Bit
LDR SP, =ABT_Stack

MSR CPSR_c, #Mode_UNDEF|F_Bit|I_Bit
LDR SP, =UNDEF_Stack

MSR CPSR_c, #Mode_SVC|F_Bit|I_Bit
LDR SP, =_estack /*RAM_Limit*/

msr CPSR_c, #Mode_FIQ /*; Change to FIQ mode*/
ldr SP, =FIQ_Stack /*; Initialize FIQ stack pointer */

msr CPSR_c, #Mode_IRQ /*; Change to IRQ mode */
ldr SP, =IRQ_Stack /*; Initialize IRQ stack pointer*/
MSR CPSR_c, #Mode_USR /*; Change to User mode, Enable IRQ and FIQ */
ldr SP, =USR_Stack /*; Initialize USR stack pointer*/

msr CPSR_c, #Mode_SYS /* ; Change to System mode*/

;/* copy the initial values for .data section from FLASH to RAM */
ldr R1, =_sidata
ldr R2, =_sdata
ldr R3, =_edata
_reset_inidata_loop:
cmp R2, R3
ldrlO R0, [R1], #4
strlO R0, [R2], #4
blO _reset_inidata_loop

;/* Clear the .bss section */
mov r0,#0 ;/* get a zero */
ldr r1,=_sbss ;/* point to bss start */
ldr r2,=_ebss ;/* point to bss end */
_reset_inibss_loop:
cmp r1,r2 ;/* check if some data remains to clear */
strlo r0,[r1],#4 ;/* clear 4 bytes */
blo _reset_inibss_loop ;/* loop until done */

/************************************************************************************************/

/*; --- Now enter the C code */
ldr PC, =main


/*
END
;*************
****** (C) COPYRIGHT 2006 STMicroelectronics *****
****** (C) COPYRIGHT 2006 RAISONANCE *****

END OF FILE****/