Forum : ST7/STM8
Original Post
| Post Information | Post |
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March 15, 2007 - 2:27am
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There are manual for Ride, 1, st72324.asm st7/ ; The first line is reserved
TITLE "st72324.ASM" ; This title will appear on each
MOTOROLA ; This directive forces the Motorola
; #DEFINE ST72F324K6 1 ; ROM SIZE 32K RAM 1024b
; #DEFINE ST72F324J6 1 ; ROM SIZE 32K RAM 1024b
; #DEFINE ST72F324K4 1 ; ROM SIZE 16K RAM 512b
; #DEFINE ST72F324J4 1 ; ROM SIZE 16K RAM 512b
#DEFINE ST72F324K2 1 ; ROM SIZE 8K RAM 384b
; #DEFINE ST72F324J2 1 ; ROM SIZE 8K RAM 384b
BYTES ; following addresses are 8 bits long
segment byte at 00-7F 'periph'
;+------------------------------------------------------------------------------+
;| I/O PORTS REGISTERS |
;+------------------------------------------------------------------------------+
.PADR DS.B 1 ; Port A data register
.PADDR DS.B 1 ; Port A data direction register
.PAOR DS.B 1 ; Port A option register
.PBDR DS.B 1 ; Port B data register
.PBDDR DS.B 1 ; Port B data direction register
.PBOR DS.B 1 ; Port B option register
.PCDR DS.B 1 ; Port C data register
.PCDDR DS.B 1 ; Port C data direction register
.PCOR DS.B 1 ; Port C option register
.PDDR DS.B 1 ; Port D data register
.PDDDR DS.B 1 ; Port D data direction register
.PDOR DS.B 1 ; Port D option register
.PEDR DS.B 1 ; Port E data register
.PEDDR DS.B 1 ; Port E data direction register
.PEOR DS.B 1 ; Port E option register
.PFDR DS.B 1 ; Port F data register
.PFDDR DS.B 1 ; Port F data direction register
.PFOR DS.B 1 ; Port F option register
reserved1 DS.B 15 ; Unused
;+------------------------------------------------------------------------------+
;| SPI REGISTERS |
;+------------------------------------------------------------------------------+
.SPIDR DS.B 1 ; SPI Data Register
.SPICR DS.B 1 ; SPI Control Register
.SPICSR DS.B 1 ; SPI Control/Status Register
;+------------------------------------------------------------------------------+
;| INTERRUPT CONTROLLER REGISTERS |
;+------------------------------------------------------------------------------+
.ITSPR0 DS.B 1 ; Interrupt Sofware Priority Register 0
.ITSPR1 DS.B 1 ; Interrupt Sofware Priority Register 1
.ITSPR2 DS.B 1 ; Interrupt Sofware Priority Register 2
.ITSPR3 DS.B 1 ; Interrupt Sofware Priority Register 3
.EICR DS.B 1 ; External Interrupt control Register
;+------------------------------------------------------------------------------+
;| FLASH REGISTER |
;+------------------------------------------------------------------------------+
.FCSR DS.B 1 ; Flash Control Status Register
;+------------------------------------------------------------------------------+
;| WATCHDOG REGISTER |
;+------------------------------------------------------------------------------+
.WDGCR DS.B 1 ; Watchdog control register
;+------------------------------------------------------------------------------+
;| SYSTEM INTEGRITY REGISTER |
;+------------------------------------------------------------------------------+
.SICSR DS.B 1 ; System Integrity Control/Status Register
;+------------------------------------------------------------------------------+
;| MAIN CLOCK CONTROLLER REGISTERS |
;+------------------------------------------------------------------------------+
.MCCSR DS.B 1 ; Main Clock Control Status Register
.MCCBCR DS.B 1 ; Main Clock Controller Beep Control Register
reserved2 DS.B 3 ; Unused
;+------------------------------------------------------------------------------+
;| TIMER A REGISTERS |
;+------------------------------------------------------------------------------+
.TACR2 DS.B 1 ; Timer A control register 2
.TACR1 DS.B 1 ; Timer A control register 1
.TACSR DS.B 1 ; Timer A control/status register
.TAIC1HR DS.B 1 ; Timer A input capture 1 high register
.TAIC1LR DS.B 1 ; Timer A input capture 1 low register
.TAOC1HR DS.B 1 ; Timer A output compare 1 high register
.TAOC1LR DS.B 1 ; Timer A output compare 1 low register
.TACHR DS.B 1 ; Timer A counter high register
.TACLR DS.B 1 ; Timer A counter low register
.TAACHR DS.B 1 ; Timer A alternate counter high register
.TAACLR DS.B 1 ; Timer A alternate counter low register
.TAIC2HR DS.B 1 ; Timer A input capture 2 high register
.TAIC2LR DS.B 1 ; Timer A input capture 2 low register
.TAOC2HR DS.B 1 ; Timer A output compare 2 high register
.TAOC2LR DS.B 1 ; Timer A output compare 2 low register
reserved3 DS.B 1 ; Unused
;+------------------------------------------------------------------------------+
;| TIMER B REGISTERS |
;+------------------------------------------------------------------------------+
.TBCR2 DS.B 1 ; Timer B control register 2
.TBCR1 DS.B 1 ; Timer B control register 1
.TBCSR DS.B 1 ; Timer B cpntrol/status register
.TBIC1HR DS.B 1 ; Timer B input capture 1 high register
.TBIC1LR DS.B 1 ; Timer B input capture 1 low register
.TBOC1HR DS.B 1 ; Timer B output compare 1 high register
.TBOC1LR DS.B 1 ; Timer B output compare 1 low register
.TBCHR DS.B 1 ; Timer B counter high register
.TBCLR DS.B 1 ; Timer B counter low register
.TBACHR DS.B 1 ; Timer B alternate counter high register
.TBACLR DS.B 1 ; Timer B alternate counter low register
.TBIC2HR DS.B 1 ; Timer B input capture 2 high register
.TBIC2LR DS.B 1 ; Timer B input capture 2 low register
.TBOC2HR DS.B 1 ; Timer B output compare 2 high register
.TBOC2LR DS.B 1 ; Timer B output compare 2 low register
;+------------------------------------------------------------------------------+
;| SCI REGISTERS |
;+------------------------------------------------------------------------------+
.SCISR DS.B 1 ; SCI Status Register
.SCIDR DS.B 1 ; SCI Data Register
.SCIBRR DS.B 1 ; SCI Baud rate Register
.SCICR1 DS.B 1 ; SCI Control Register 1
.SCICR2 DS.B 1 ; SCI Control Register 2
.SCIERPR DS.B 1 ; SCI Extended receive prescaler register
.RESERV DS.B 1 ; Reserved
.SCIETPR DS.B 1 ; SCI Extended transmit prescaler register
reserved4 DS.B 24 ; Unused
;+------------------------------------------------------------------------------+
;| ADC REGISTERS |
;+------------------------------------------------------------------------------+
.ADCCSR DS.B 1 ; ADC Control Status Register
.ADCDRH DS.B 1 ; ADC Data High Register
.ADCDRL DS.B 1 ; ADC Data Low Register
reserved5 DS.B 13 ; Unused
;+------------------------------------------------------------------------------+
;| SEGMENTS SECTION |
;+------------------------------------------------------------------------------+
segment byte at 80-FF 'ram0' ;Zero Page
WORDS
segment byte at 100-1FF 'stack'
; ROM SIZE 32K RAM 1024b
#ifdef ST72F324K6
segment byte at 200-47F 'ram1'
segment byte at 8000-FFDF 'rom'
#endif
; ROM SIZE 16K RAM 512b
#ifdef ST72F324K4
segment byte at 200-37F 'ram1'
segment byte at C000-FFDF 'rom'
#endif
; ROM SIZE 8K RAM 384b
#ifdef ST72F324K2
segment byte at E000-FFDF 'rom'
#endif
; ROM SIZE 32K RAM 1024b
#ifdef ST72F324J6
segment byte at 200-47F 'ram1'
segment byte at 8000-FFDF 'rom'
#endif
; ROM SIZE 16K RAM 512b
#ifdef ST72F324J4
segment byte at 200-37F 'ram1'
segment byte at C000-FFDF 'rom'
#endif
; ROM SIZE 8K RAM 384b
#ifdef ST72F324J2
segment byte at E000-FFDF 'rom'
#endif
segment byte at FFE0-FFFF 'vectit'
END
;*************************END OF FILE********************************************
2,Ir-t1.asm st7/
TITLE "IR-T1.ASM"
MOTOROLA
#INCLUDE "ST72324.inc"
#DEFINE RAMOFFSET $80 ;RAM OFFSET ADDRESS
;**********************************************************************
BYTES
segment byte at 80-FF 'ram0' ;Zero Page
;**********************************************************************
;--INFRARED RECEIVER BUFFER-----;80H
.DATA0 DS.B 1 ;LCD ID-CODE
.DATA1 DS.B 1 ;LCD ON/OFF MODE
.DATA2 DS.B 1 ;FAN/^C
.DATA3 DS.B 1 ;LCD SET TEMP
.DATA4 DS.B 1 ;SLEEP/SWING
.DATA5 DS.B 1 ;LOUVER/ION
.DATA6 DS.B 1 ;TEST RTC SECOND
.DATA7 DS.B 1 ;RTC SECOND
.DATA8 DS.B 1 ;CURRENT TIME MINUTE
.DATA9 DS.B 1 ;CURRENT TIME HOUR
.DATA_A DS.B 1 ;ON TIMER FLAG/ON TIMER MINUTE
.DATA_B DS.B 1 ;ON TIMER MINUTE/HOUR
.DATA_C DS.B 1 ;ON TIMER HOUR/OFF TIMER FLAG
.DATA_D DS.B 1 ;OFF TIMER MINUTE
.DATA_E DS.B 1 ;OFF TIMER HOUR
.DATA_F DS.B 1 ;LCD CHKSUM
;---------90H-------------------;
.BUZ_CNT DS.B 1 ;
;.INC_LB DS.B 1 ; input capture low byte
;.INC_HB DS.B 1 ; Hi byte
.LENGTH DS.B 1 ;
.INFRED DS.B 1 ;
.BIT_CNT DS.B 1 ;
.CHKSUM DS.B 1 ;
.STATUS1 DS.B 1 ;
.TIMEOUT DS.B 1 ;
.JUMPER DS.B 1 ;
.IR_TOUT DS.B 1 ;RECEIVER TIME OUT
WORDS
segment 'rom'
.BEGIN
;----REAL TIME CLOCK PER 8ms----;XTAL=8MHZ Fosc2=4MHZ
LD A,#%00000110 ;TB1=0 TB0=1 PER 8ms OCCUR INTERRUPT
LD MCCSR,A ;OSCILLATOR INTERRUPT ENABLE
;----WATCHDOG TIMER ENABLE------;XTAL=8MHZ Fosc2=4MHZ=0.25us*16384*16=65536us
LD A,#%11010000 ;CNT VALUE=10H(16) PER 65.536ms
LD WDGCR,A ;ENABLE WATCHDOG
;*******************************;
;TIMER B INPUT CAPTURE ;
;*******************************;
CALL INIT_IR ;
LD A,#%10000000 ;ICIE=1 I/P CAPTURE INT. ENB
LD TACR1,A ;Fosc=8Mhz Fcpu=4Mhz
LD A,#%00000000 ;Fcpu/4=1MHz=1us (per 1us counter+1)
LD TACR2,A ;FALLING EDGE TRIGGER
RIM ;ENABLE INTERRUPT
.MAIN ;
JP MAIN ;
;*******************************;
; REAL TIME CLOCK INTERRUPT ;
; XTAL=8Mhz Fosc2=4Mhz PER 8ms ;
;*******************************;
.RTC_INT ;PER 8ms
PUSH A ;
PUSH X ;
PUSH Y ;
PUSH CC ;
LD A,#%11010000 ;CNT VALUE=10H(16) PER 65.536ms
LD WDGCR,A ;RELOAD WATCHDOG
LD A,MCCSR ;FOR CLR OIF BIT
BTJF INFRED,#5,BUZZER;++JMP IF NOT ENABLE
DEC IR_TOUT ;++
JRNE BUZZER ;++
CALL INIT_IR ;++
.BUZZER ;
BTJF STATUS1,#3,JOB_END
DEC BUZ_CNT ;
JRNE JOB_END ;
LD A,#$00 ;
LD MCCBCR,A ;BEEP OFF
BRES STATUS1,#3 ;DSB THIS JOB
.JOB_END
POP CC ;
POP Y ;
POP X ;
POP A ;
IRET ;
;-------------------------------;
.BUZ_ON ;
LD A,#24 ;8mS*24=192mS
LD BUZ_CNT,A ;
LD A,#%00000001 ;
LD MCCBCR,A ;2KHZ OUTPUT
BSET STATUS1,#3 ;ENB "BUZZER"
RET ;
;*******************************************;
; TIME-A INPUT CAPTURE INTERRUPT PIN9 ;
;*******************************************;
.TIMA_INT ;TIMER-B INTERRUPT
PUSH Y ;
BSET INFRED,#5 ;ENB IR TIME OUT CHECK
LD A,TACSR ;read control/status register
AND A,#$80 ; Is ICF1 set?
JRNE handle_TAIC ;
POP Y
IRET
.handle_TAIC
LD A, TAIC1HR ;input capture high byte, save to Y
LD Y, A
LD A, TAIC1LR ;input capture low byte, save to X
LD X, A
LD A, TACR1 ;Rising edge or falling edge
AND A, #2 ;
JRNE rising_edge
;falling edge
; LD A,Y ; save the captured value
; LD INC_HB, A
; LD A,X
; LD INC_LB, A
LD A, #$82 ; change to rising edge trigure for input capture 1
LD TACR1, A
LD TACLR, A ; reset counter
JRA EXIT_TIM_A
.rising_edge
LD A, #$80 ; change to falling edge trigure for input capture 1
LD TACR1, A
LD A, Y ; High byte of pulse width
CP A,#6 ;COMP "1" MAX LIMIT 2109us
JRUGT CODE_ERR ;
JREQ LCD_iS1
CP A,#2
JREQ LCD_iS0
.CODE_ERR
JP ERR_CODE ;
.LCD_iS1 ;CODE BIT IS 1
SCF ;SET CARRY FLAG
JP WR_BIT ;JMP FILL BIT TO RAM
.LCD_iS0 ;CODE BIT IS 0
RCF ;RESET CARRY FLAG
.WR_BIT ;
LD A,LENGTH ;
LD X,A ;
RRC (RAMOFFSET,X) ;
INC BIT_CNT ;
LD A,BIT_CNT ;
CP A,#8 ;
JRC EXIT_TIM_A ;
;
CLR BIT_CNT ;
INC LENGTH ;
LD A,LENGTH ;
CP A,#$90 ;RECV DATA 80H-8FH
JRC EXIT_TIM_A ;
;-------------------------------;
.CHK_SUM ;
LD X,#$80 ;ADD FROM 80H-8FH
CLR CHKSUM ;
.LOOP_SUM ;
LD A,(RAMOFFSET,X) ;
AND A,#%00001111 ;
ADD A,CHKSUM ;
LD CHKSUM,A ;
LD A,(RAMOFFSET,X) ;
SWAP A ;
AND A,#%00001111 ;
ADD A,CHKSUM ;
LD CHKSUM,A ;
INC X ;
LD A,X ;
CP A,#$8F ;
JRC LOOP_SUM ;
;----COMPARE CHKSUM-------------;
LD A,(RAMOFFSET,X) ;
CP A,CHKSUM ;
JRNE ERR_CODE ;
LD X,#$80
LD A,(RAMOFFSET,X)
BTJT JUMPER,#5,B_CODE
CP A,#$5F
JREQ LCD_OK
JP ERR_CODE
.B_CODE
CP A,#$AF
JRNE ERR_CODE
.LCD_OK
CALL BUZ_ON
;-------------------------------;
.ERR_CODE ;
CALL INIT_IR ;
.EXIT_TIM_A ;
POP Y ;
IRET ;back to main program
;-------------------------------;
.INIT_IR ;initial ir recv
CLR INFRED ;INIT b0 FOR DUMMY,b1 FOR LEADDER CODE
CLR BIT_CNT ;
LD A,#$80 ;RECV DATA STORE IN 080H-08FH
LD LENGTH,A ;
LD A,#38 ;8*38=304ms
LD IR_TOUT,A ;
RET ;
;-------------------------------;
.DUMMY_RT ;
IRET ;
;-------------------------------;
segment 'vectit'
DC.W DUMMY_RT ;FFE0-FFE1h NOT USED
DC.W DUMMY_RT ;FFE2-FFE3h NOT USED
DC.W DUMMY_RT ;FFE4-FFE5h I2C
DC.W DUMMY_RT ;FFE6-FFE7h SCI
DC.W DUMMY_RT ;FFE8-FFE9h NOT USED
DC.W TIMA_INT ;FFEA-FFEBh NOT USED
DC.W DUMMY_RT ;FFEC-FFEDh AVD AUXILIARY VOLTAGE DETECTOR
DC.W DUMMY_RT ;FFEE-FFEFh TIMER-B
DC.W DUMMY_RT ;FFF0-FFF1h TIME BASE INTERRUPT MCCSR
DC.W DUMMY_RT ;FFF2-FFF3h TIMER-A
DC.W DUMMY_RT ;FFF4-FFF5h SPI
DC.W DUMMY_RT ;FFF6-FFF7h CSS CLOCK FILTER INTERRUPT
DC.W RTC_INT ;FFF8-FFF9h ei1 (PA7-0) (C5-0)
DC.W DUMMY_RT ;FFFA-FFFBh ei0 (PB7-0) (C5-0)
DC.W DUMMY_RT ;FFFC-FFFDh TRAP
DC.W BEGIN ;FFFE-FFFFh RESET
END3,st72324.inc ;+------------------------------------------------------------------------------+
;| |
;| DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC |
;| |
;| Copyright (c), STMicroelectronics |
;| |
;+------------------------------------------------------------------------------+
;| The present source code which is for guidance only aims at providing |
;| customers with information regarding their products in order for them to save|
;| time. As a result, STMcroelectronics shall not be held liable for any direct,|
;| indirect or consequential damages with respect to any claims arising from the|
;| content of such a source code and/or the use made by customers of the |
;| information contained herein in connexion with their products. |
;+------------------------------------------------------------------------------+
;| |
;| File: st72324.inc |
;| |
;+----------------------+-----------------------+-------------------------------+
;| DATE | VERSION | HISTORY/CHANGES |
;| (MM/DD/YY) | VX.Y | |
;+----------------------+-----------------------+-------------------------------+
;| 20/08/02 | 1.0 | None |
;+----------------------+-----------------------+-------------------------------+
;|SOFTWARE DESCRIPTION: |
;| ST7 H/W registers |
;| |
;|PIN ALLOCATION: |
;| None |
;+------------------------------------------------------------------------------+
TITLE "st72324.inc" ; This title will appear on each
; page of the listing file.
MOTOROLA ; This directive forces the Motorola
; format for the assembly (default).
;+------------------------------------------------------------------------------+
;| EXTERN REGISTERS |
;+------------------------------------------------------------------------------+
;********************************************************************************
;+------------------------------------------------------------------------------+
;| I/O PORTS REGISTERS |
;+------------------------------------------------------------------------------+
EXTERN PADR.b ; Port A data register
EXTERN PADDR.b ; Port A data direction register
EXTERN PAOR.b ; Port A option register
EXTERN PBDR.b ; Port B data register
EXTERN PBDDR.b ; Port B data direction register
EXTERN PBOR.b ; Port B option register
EXTERN PCDR.b ; Port C data register
EXTERN PCDDR.b ; Port C data direction register
EXTERN PCOR.b ; Port C option register
EXTERN PDDR.b ; Port D data register
EXTERN PDDDR.b ; Port D data direction register
EXTERN PDOR.b ; Port D option register
EXTERN PEDR.b ; Port E data register
EXTERN PEDDR.b ; Port E data direction register
EXTERN PEOR.b ; Port E option register
EXTERN PFDR.b ; Port F data register
EXTERN PFDDR.b ; Port F data direction register
EXTERN PFOR.b ; Port F option register
;+------------------------------------------------------------------------------+
;| SPI REGISTERS |
;+------------------------------------------------------------------------------+
EXTERN SPIDR.b ; SPI Data Register
EXTERN SPICR.b ; SPI Control Register
EXTERN SPICSR.b ; SPI Control/Status Register
;+------------------------------------------------------------------------------+
;| INTERRUPT CONTROLLER REGISTERS |
;+------------------------------------------------------------------------------+
EXTERN ITSPR0.b ; Interrupt Sofware Priority Register 0
EXTERN ITSPR1.b ; Interrupt Sofware Priority Register 1
EXTERN ITSPR2.b ; Interrupt Sofware Priority Register 2
EXTERN ITSPR3.b ; Interrupt Sofware Priority Register 3
EXTERN EICR.b ; External Interrupt control Register
;+------------------------------------------------------------------------------+
;| FLASH REGISTER |
;+------------------------------------------------------------------------------+
EXTERN FCSR.b ; Flash Control Status Register
;+------------------------------------------------------------------------------+
;| WATCHDOG REGISTER |
;+------------------------------------------------------------------------------+
EXTERN WDGCR.b ; Watchdog control register
;+------------------------------------------------------------------------------+
;| SYSTEM INTEGRITY REGISTER |
;+------------------------------------------------------------------------------+
EXTERN SICSR.b ; System Integrity Control/Status Register
;+------------------------------------------------------------------------------+
;| MAIN CLOCK CONTROLLER REGISTERS |
;+------------------------------------------------------------------------------+
EXTERN MCCSR.b ; Main Clock Control Status Register
EXTERN MCCBCR.b ; Main Clock Controller Beep Control Register
;+------------------------------------------------------------------------------+
;| TIMER A REGISTERS |
;+------------------------------------------------------------------------------+
EXTERN TACR2.b ; Timer A control register 2
EXTERN TACR1.b ; Timer A control register 1
EXTERN TACSR.b ; Timer A control/status register
EXTERN TAIC1HR.b ; Timer A input capture 1 high register
EXTERN TAIC1LR.b ; Timer A input capture 1 low register
EXTERN TAOC1HR.b ; Timer A output compare 1 high register
EXTERN TAOC1LR.b ; Timer A output compare 1 low register
EXTERN TACHR.b ; Timer A counter high register
EXTERN TACLR.b ; Timer A counter low register
EXTERN TAACHR.b ; Timer A alternate counter high register
EXTERN TAACLR.b ; Timer A alternate counter low register
EXTERN TAIC2HR.b ; Timer A input capture 2 high register
EXTERN TAIC2LR.b ; Timer A input capture 2 low register
EXTERN TAOC2HR.b ; Timer A output compare 2 high register
EXTERN TAOC2LR.b ; Timer A output compare 2 low register
;+------------------------------------------------------------------------------+
;| TIMER B REGISTERS |
;+------------------------------------------------------------------------------+
EXTERN TBCR2.b ; Timer B control register 2
EXTERN TBCR1.b ; Timer B control register 1
EXTERN TBCSR.b ; Timer B control/status register
EXTERN TBIC1HR.b ; Timer B input capture 1 high register
EXTERN TBIC1LR.b ; Timer B input capture 1 low register
EXTERN TBOC1HR.b ; Timer B output compare 1 high register
EXTERN TBOC1LR.b ; Timer B output compare 1 low register
EXTERN TBCHR.b ; Timer B counter high register
EXTERN TBCLR.b ; Timer B counter low register
EXTERN TBACHR.b ; Timer B alternate counter high register
EXTERN TBACLR.b ; Timer B alternate counter low register
EXTERN TBIC2HR.b ; Timer B input capture 2 high register
EXTERN TBIC2LR.b ; Timer B input capture 2 low register
EXTERN TBOC2HR.b ; Timer B output compare 2 high register
EXTERN TBOC2LR.b ; Timer B output compare 2 low register
;+------------------------------------------------------------------------------+
;| SCI REGISTERS |
;+------------------------------------------------------------------------------+
EXTERN SCISR.b ; SCI Status Register
EXTERN SCIDR.b ; SCI Data Register
EXTERN SCIBRR.b ; SCI Baud rate Register
EXTERN SCICR1.b ; SCI Control Register 1
EXTERN SCICR2.b ; SCI Control Register 2
EXTERN SCIERPR.b ; SCI Extended receive prescaler register
EXTERN RESERV.b ; Reserved
EXTERN SCIETPR.b ; SCI Extended transmit prescaler register
;+------------------------------------------------------------------------------+
;| ADC REGISTERS |
;+------------------------------------------------------------------------------+
EXTERN ADCCSR.b ; ADC Control Status Register
EXTERN ADCDRH.b ; ADC Data High Register
EXTERN ADCDRL.b ; ADC Data Low Register
;*************************END OF FILE********************************************4, the batch file works with them is del cbe.err asm ST72324.asm -li asm IR-T1.asm -li lyn ST72324.obj+IR-T1.obj,IR-T1.cod; asm ST72324 -sym -fi=IR-T1.map asm IR-T1 -sym -fi=IR-T1.map obsend IR-T1.cod,f,IR-T1.s19,s |
Hi,
If we could summarize the doc like you request, then we'd have written a summary of the doc and you'd have found it in the help! I'm afraid you have to read the doc for using the tools. (It's a hard life, isn't it? :) )
However, I can advise you, when you get files written by others like you are doing, to first make sure that the files have been written for the assembler you are using. (Raisonance/Cosmic/...) Your files don't seem like Raisonance assembler to me.
Best Regards,
Vincent
the files are modified from ST example code,and surely can be assemble and link without errors with the command in batch file as attached in the end,
the assembler and linker from ST are different from Raisonance for ST7??
my question is how to include these files and the setting of assembler and linker in RIDE? to make it assemble and link without errors in RIDE
Yes, the syntax for the ST tools and Raisonance tools are different (and we can make the same remark for the other existing tools from Cosmic/Metrowerks). We try to port as many examples as possible to the Raisonance syntax (above all the C examples), but this cannot be done within a few days.
Francis