Topic : Excessive optimization again?

Forum : ST7/STM8

Original Post
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October 14, 2009 - 11:42am
Guest

I have the following function:

UBYTE ReadByte(UBYTE Addr)
{
   // Backup Interrupt enable flag and disable interrupts
   retBool bSPIEFlag = SPIE;
   SPIE = false;

   RTCCS = IOALOn;
   SPIDR = RTC_CMD_Read | Addr;
   WAIT_WHILE(!SPIF);
   RTCCS = IOALOff;

   SPIDR; // Touch SPIDR to clear Flag before (possibly) re-enabling interrupts
   SPIE = bSPIEFlag; // Restore Interrupt state before returning

   return SPIDR;
}

the SPIDR = RTC_CMD_Read | Addr; assignment is moved to the start of the routine before the hardware CS line is asserted low.

              ; FUNCTION ReadByte (BEGIN)
              ; Register X is assigned to parameter Addr
              ; SOURCE LINE # 185 
0000 B721                              LD     SPIDR,A
              ; Y is assigned to bSPIEFlag
              ; SOURCE LINE # 188 
0002 4F                                CLR    A
0003 0F2201                            BTJF   SPIE,?NXT_0004
0006 4C                                INC    A
0007         ?NXT_0004:
0007 9097                              LD     Y,A
              ; SOURCE LINE # 189 
0009 1F22                              BRES   SPIE
              ; SOURCE LINE # 191 
000B 1706                              BRES   RTCCS
000D         ?WHILE_0001:
              ; SOURCE LINE # 193 
000D 0E2303                            BTJT   SPIF,?NXT_0005
0010 9D                                NOP    
0011 20FA                              JRA    ?WHILE_0001
0013         ?NXT_0005:
              ; SOURCE LINE # 194 
0013 1606                              BSET   RTCCS
              ; SOURCE LINE # 196 
0015 BE21                              LD     X,SPIDR
              ; SOURCE LINE # 197 
0017 905D                              TNZ    Y
0019 2704                              JREQ   ?NXT_0006
001B 1E22                              BSET   SPIE
001D 2002                              JRA    ?NXT_0007
001F         ?NXT_0006:
001F 1F22                              BRES   SPIE
0021         ?NXT_0007:
              ; SOURCE LINE # 199 
0021 B621                              LD     A,SPIDR
0023 81                                RET    
              ; Addr         unsigned char  (size=1). Register parameter(A) in PAGE0
              ; bSPIEFlag    unsigned char  (size=1). Automatic variable  in PAGE0

              ; FUNCTION ReadByte (END)

I am using the standard ST7 header that's distributed with the compiler, so SPIDR is an hreg. Re-declaring SPIDR as 'volatile hreg' makes no difference, but I guess hreg is already treated as volatile. Am I correct in expecting the compiler not to move the SPIDR assignment?

Compiler command line:

RCSTM8 COMPILER V2.25.09.238, COMPILATION OF MODULE RTC       
OBJECT MODULE PLACED IN Release\rtc.o
COMPILER INVOKED BY: OBJECT(Release\rtc.o) PIN(C:\Program Files\Raisonance\Ride\inc\ST7) PIN(C:\Program Files\Raisonance\Ride\inc) WRV(0) ST7SET DGC(data) DLC(page0) OT(7,SPEED) PR(Release\rtc.lst) CD CO SB NOIS CD CO SB SMOB ET(CHAR)
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October 14, 2009 - 3:20pm
Raisonance Support Team

Bug fixed: volatile variable are moved anymore.

Fix will be available in next RKit-STM8 release.