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January 20, 2010 - 12:27am
Guest |
I'm using the latest ST7/STM8 toolkit (2.26.09.0317) with STM8S208RB device and also applied the patch from December 14th, 2009. I have encountered an issue with the backup of CPU registers during interrupt processing.
It seems that the condition code register (CCR) is not backed properly upon interrupt request.
Accumulator A and index registers X and Y are being pushed into and popped from the stack but there is no push of the condition code register (CCR).
This sometimes leads to an unexpected behaviour in my application if the flags (V, H, N, Z, C) of the condition code register (CCR) are changed during the interrupt service routine.
If I put inline assembler instruction PUSH CC (0x8A) at the beginning and POP CC (0x86) at the end of the ISR it works fine.
Best regards,
Paetze
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Hi Paul,
That's an "interesting" issue.
You do not mention your device type, but as you mention a "V" flag I guess that you are using an STM8S.
When an interrupt occurs, the STM8 will automatically push the registers (including CC) and restore them after the IRET instruction. So the compiler is not involved in the process.
However if you verified that adding a PUSH CC/POP CC fixes the issue, we have to dig a bit deeper in order to understand the root cause of the problem.
Can you send us a (minimal) example that shows the problem, as well as some instructions for reproducting the problem? We will have a look at it in our labs.
Thanks,
Bruno