Forum : ST7/STM8
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March 3, 2010 - 11:33am
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Hi, my SPI code for parity bit control work well, but if let alone. If I add Lart, LT, ADC and all what I need, it dont work as it must be: ST7lite39 on REva 2.10 dont response ACK (0x06) or NACK (0x15) but repeat the input MOSI byte... it seems to be unwrittable the SPIDR register in that moment, because if I defeat SPI_PutByte nothing change... Quote:
What could I control? Any idea? Thx. |
Hi,
for your knowledge:
it work with Master and Slave with SPI_Phase at 1. If you use SPI_Phase at 0 you could have problems.
I only had to give (SPI phase 1) by
How could I use "CLK_PP_Value - Selects the clock polarity and clock phase" in it?
Program dislike it's use.
Thanks
Hello Chiesa,
This problem looks very much processor-related, and we will only be helpful concerning development tools. I suggest that you turn to the ST support people in order to get help specific to your problem.
Regards,
Bruno
Hi, what I could understand is that I must know before how many byte my cpu is receiving and pass a initialize "SPI_GetBuffer" to initialize the buffer reception.
After in the ISR of SPI I must use "SPI_IT_Function" to capture data input to the buffer (rx or tx as needed).
Is it right?
The problem was removed writing a FlagClean function as first function in the SPI ISR to clean the interrupt bit in the register.
I'm modifying your SPI IT function to achieve my desired protocol... ;)
Thanks.