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May 25, 2012 - 5:50pm
Guest |
Hello,
I need to know when the SIM instruction sets the disable interrupt (CC.I1) flag in the instruction.
We have had issues with other processors where the flag is set at the end of the instruction. If this is the case, SIM can be executed, a low level interrupt can happen, but the flag is set, stopping high level interrupts from happening.
The worst case scenario is the high level interrupt doesn't execute until the duration of the low level interrupt, and the execution of the 'critical code' until the interrupts are enabled again.
Where can I find this timing data?
Does my explanation make sense?
Thanks in advance,
GeorgeR
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Hi,
The STM8 core instructions are atomic (executed or not) and that the execution speed will not be impacted in case an interrupt occurs.
Concerning priority inversion, this is a classic topic that should be adressed directly in your application.
However, we have limited knowledge about microcontroller internals, and even less about their peripherals.
We suggest that you contact the chip manufacturer's support team for more help on this issue.
Regards,