Topic : Problem with RLink Pro and STR750?

Forum : ARM

Original Post
Post Information Post
April 3, 2007 - 9:53pm
Guest

Dear Sir,

I found that using too slow speed for HCLK cause the Rlink Pro to behave erratically. REVA V2.0, STR750FV2, HCLK = 2MHz.

I want to use 32MHz for all of the internal clocks: CK_SYS, HCLK, PCLK, CK_TIM.

At start, the CPU is clocked by FREEOSC (circa 5MHz). Then, following ST guidelines, I switch on the 4M crystal osc, then I select 4M as the CK_SYS, then I should set HCLK/PCLK/CK_TIM dividers BEFORE turning on the PLL (as per your examples, btw). The PLL will work at 64MHz, so I need at least a / 2 divisor for HCLK...but, before turning on PLL, the HCLK will be set to 2MHz and the RLink will constantly hang if Stepped. This happens with your examples, too, so I am quite sure it's not my fault.

Any idea?

Thank you

Romano
Replies
Post Information Post
+1
0
-1
April 4, 2007 - 11:56am
Raisonance Support Team

Hi,

Please give us more information on the way to reproduce the problem with our examples...

Which Build Number of RIDE are you using?
Which board are you using?
If it's a custom board, can we have the schematic?
Which example project are you using?
How do you configure it? (boot mode, etc.)
At which point does it fail?
What operations (go, stop, step, breakpoints, etc.) do you perform before that?

Best Regards,

Vincent
+1
0
-1
April 4, 2007 - 2:56pm
Guest

REVA v2.0 with STR750F module
RIDE Version 06.10.22 BN746-ST7-ARM-80C51-P1-STR750
ARM mode, OPT = 0

int main(void)
{
        // WAIT FOR 4M OSC
        for(;;)
   {
      MRCC->CLKCTL &= ~NCKDF;               // Reset del bit
      if((MRCC->CLKCTL & NCKDF) == 0) break;   // Attesa che resti a zero
   }

        // WAIT FOR 4M OSC STABLE
   // Attesa BCOUNTF == 1 (nello stesso tempo NCKDF deve essere rimasto a zero)
   for(;;)
   {
      while((MRCC->RFSR & BCOUNTF) == 0);
      if((MRCC->CLKCTL & NCKDF) == 0) break;   // Esce se bit e' rimasto a zero
      MRCC->CLKCTL &= ~NCKDF;               // Altrimenti, reset del bit e riprova
   }
      
        // SWITCH CK_SYS FORM FREEOSC TO 4MOSC
   // Commuta da CK_PLL1 (settato su FREEOSC) a CK_OSC (settato su CK_OSC4M)
   MRCC->CLKCTL |= CKSEL;   
   if((MRCC->CLKCTL & CKSEL) == 0) for(;;);   // blocco del programma
   
        // SET CLOCK DIVISOR BEFORE TURNING ON PLL
   // *** ATTENZIONE DEBUGGER ***
   // L'istruzione seguente mette il clock HCLK a 2MHz (prima di attivare il PLL a 64MHz).
   // Per qualche strana ragione il debugger RLink Pro smette di funzionare se messo in single step
   // Se invece la hw_init() viene eseguita come Step Over, non ci sono quasi mai problemi.
   MRCC->CLKCTL &= ~0x0000001f;            // Azzera i 5 bit dei prescaler
   MRCC->CLKCTL |= HPRESC0;               // A cascata anche PCLK e CK_TIM saranno = HCLK
        // ^^^^^^^^^^^^^^ OFFENDING INSTRUCTION

   // A questo punto la CPU va con i 4MHz dell'oscillatore (CK_SYS)
   // Il PLL per default e' a 16x (4MHz x 16 = 64MHz)
   MRCC->CLKCTL |= PLLEN;                  // Abilita PLL
   while((MRCC->CLKCTL & LOCK) == 0);          // Attesa LOCK   
   MRCC->CLKCTL &= ~CKSEL;                     // Commuta il clock CPU: CK_SYS = CK_PLL1
...
...
...

If I put the above code in a subroutine, and I avoid to Step Into, all is ok. If I step into the subroutine, I get several messages:

"Memory bus stalled.." "Out of range" or simply crash.

Regards

Romano
+1
0
-1
April 4, 2007 - 4:45pm
Raisonance Support Team

Hi,

You said that the problem was occurring with one of our examples. Can you tell me which one?

Vincent
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0
-1
April 4, 2007 - 7:05pm
Guest

Try c:\ride\lib\strx\str75x_lib\examples\tb\example1

in main.c, there is the following subroutine:

void MRCC_Configuration(void)
{
  /* MRCC system reset(for debug purpose) */
  MRCC_DeInit();

  /* Wait for OSC4M start-up */
  OSC4MStartUpStatus = MRCC_WaitForOSC4MStartUp();

  if(OSC4MStartUpStatus == SUCCESS)
  {
    /* Set HCLK to 60 MHz */
    MRCC_HCLKConfig(MRCC_CKSYS_Div1);
...

Modify last line to:

MRCC_HCLKConfig(MRCC_CKSYS_Div2);

since I cannot go to 64MHz (outside FLASH limit).

Then step over it.

However, I found that stepping IN the MRCC_DeInit(); found some lines above,produces the same result.

Regards
+1
0
-1
April 12, 2007 - 5:44pm
Guest

No news?
+1
0
-1
April 13, 2007 - 10:38am
Raisonance Support Team

Hi,

Sorry for the late answer. I thought you had answered yourself. (which if fact you have)

The STR750 JTAG TAP uses the CPU clock. Therefore, it's not surprising that the RLink loses the com while you are changing the clock, because when doing this, there is probably a period of time during which there is no clock at all.

So I'm afraid there is nothing we can do. You'll have to step over it and trust the ST library for this particular part of the application, sorry.

Best Regards,

Vincent