Hi Vincent,

Pratibha here again. Last time I posted letter regarding Dongle problem. I borrowed new RLink dongle and i am able to program.
When dongle started giving problem I installed RIDE 6.10.21(BN 743). I have not switched over to Ride7.

I am developping a data acquisition system using STR710FZ2. I want to acquire samples at 100kHz rate & write data to CF. Here ADC needs 10uS delay after I select channel number & gain. I create this delay using by programming Timer2 in OCA(output compare mode) monoshot mode. Code is working fine but at its own speed. I acquired for One second & found that I have very few samples. Then I went through code's listing & came to know that Timer2 ISR itself is taking much more than 10uS.

I dont know why so much code is generated for simple functions? Inline function like

void EIC_IRQConfig(FunctionalState NewState) is creating hell lot of code.

I am attaching C code & listing code also. Is compiler is generating proper code?
To improve the speed I tried optimization of level 2 & size. It compiled well but is not working. Means system just sits idle.

I even tried pointers to EIC, GPIO, Timer2 registers & outputting exact values instead of using lib functions. But no change in code size.

This code has really put lid on my thoughts. Feeling hopeless. While designing I only concentrated on processor speed, no of IO pins, timers, multiple UART ports, no need for glue logic to interface CompactFlash.
Now when I looked into instruction Cycle timing, each will take atleast 2-3 processor clock cycles. And compiler is generating round-about code.
Is it possible to write assembly code at some critical places ? How should I know which all registers are free for use???

Please go throgh this & try to compile at your place & let me suggest something.
Thanks in advance for your time.

// ------------ C Code Start-----------------------------------------
main()
{
InitVariables();
InitDevice();
while(1)
{
if(Timer2IsrReturned == NO) return;

index = ChFiFo[ChRdIndex];
if(index >= 50) return;

SetChannel(index);
SetGain(index);

// Set Timer2 for 10uS delay
TIM2->CNTR = 0xFFFC;
TIM2->OCAR = 500; // Mux, pga settling time 10 uS
EIC_IRQChannelConfig( T2TIMI_IRQChannel, ENABLE );
}
}

void T2TIMI_IRQHandler(void)
{
u16 _SR;
_SR = TIM2->SR;

if((_SR & 0x4000) == 0x4000)
{
TIM2->SR = ~(0x4000);

Timer2IsrReturned = NO;

// Send SOC & forget it
EIC_IRQConfig(DISABLE);
GPIO_BitWrite(GPIO2, R_C, 0); // P2.5
delay(1); // min 80nS delay
GPIO_BitWrite(GPIO2, R_C, 1); // P2.5
EIC_IRQConfig(ENABLE);

spi_count++;
if(spi_count >= (SPI_FIFODepth+1)) spi_count = 0;

Timer2IsrReturned = YES; // now its ready for next SOC

// disable this timer2
EIC_IRQChannelConfig( T2TIMI_IRQChannel, DISABLE );

}

}

// ------------ C Code End -----------------------------------------

// ------------ Listing Code start -----------------------------------------

void T2TIMI_IRQHandler(void)
{
590: e92d4070 stmdb sp!, {r4, r5, r6, lr}
u16 _SR;
static u16 value;
static int apm_setling_or_converting = AmpSettling;

static int old_count = 1;

_SR = TIM2->SR;
594: e3a0520e mov r5, #-536870912 ; 0xe0000000
598: e2852a0b add r2, r5, #45056 ; 0xb000
59c: e1d231bc ldrh r3, [r2, #28]

if((_SR & 0x4000) == 0x4000)
5a0: e3130901 tst r3, #16384 ; 0x4000
5a4: 08bd8070 ldmeqia sp!, {r4, r5, r6, pc}
{
TIM2->SR = ~(0x4000);
5a8: e3e03901 mvn r3, #16384 ; 0x4000
5ac: e1c231bc strh r3, [r2, #28]

Timer2IsrReturned = NO;
5b0: e3a06000 mov r6, #0 ; 0x0
5b4: e59f3098 ldr r3, [pc, #152] ; 654 <.text+0x654>
5b8: e5c36000 strb r6, [r3]
* Return : None
*******************************************************************************/
inline void EIC_IRQConfig(FunctionalState NewState)
{
if (NewState==ENABLE) EIC->ICR |= 0x0001; else EIC->ICR &= ~0x0001;
5bc: e3a04102 mov r4, #-2147483648 ; 0x80000000
5c0: e1a04a44 mov r4, r4, asr #20
5c4: e5943000 ldr r3, [r4]
5c8: e3c33001 bic r3, r3, #1 ; 0x1
5cc: e5843000 str r3, [r4]

// Send SOC & forget it
EIC_IRQConfig(DISABLE);
GPIO_BitWrite(GPIO2, R_C, 0); // P2.5
5d0: e2855a05 add r5, r5, #20480 ; 0x5000
5d4: e1a00005 mov r0, r5
5d8: e3a01005 mov r1, #5 ; 0x5
5dc: e1a02006 mov r2, r6
5e0: ebfffffe bl 5e0

delay(1);
5e4: e3a00001 mov r0, #1 ; 0x1
5e8: ebfffffe bl 5e8

GPIO_BitWrite(GPIO2, R_C, 1); // P2.5
5ec: e1a00005 mov r0, r5
5f0: e3a01005 mov r1, #5 ; 0x5
5f4: e3a02001 mov r2, #1 ; 0x1
5f8: ebfffffe bl 5f8
* Return : None
*******************************************************************************/
inline void EIC_IRQConfig(FunctionalState NewState)
{
if (NewState==ENABLE) EIC->ICR |= 0x0001; else EIC->ICR &= ~0x0001;
5fc: e5943000 ldr r3, [r4]
600: e3833001 orr r3, r3, #1 ; 0x1
604: e5843000 str r3, [r4]
EIC_IRQConfig(ENABLE);

// spi_count is increased whenever SOC is sent, bcz that much data is in SPI FIFO
spi_count++;
608: e59f1048 ldr r1, [pc, #72] ; 658 <.text+0x658>
60c: e5d12000 ldrb r2, [r1]
610: e2822001 add r2, r2, #1 ; 0x1
614: e20220ff and r2, r2, #255 ; 0xff
618: e5c12000 strb r2, [r1]
if(spi_count >= (SPI_FIFODepth+1)) spi_count = 0;
61c: e59f3038 ldr r3, [pc, #56] ; 65c <.text+0x65c>
620: e5d33000 ldrb r3, [r3]
624: e2833001 add r3, r3, #1 ; 0x1
628: e1520003 cmp r2, r3
62c: a5c16000 strgeb r6, [r1]

Timer2IsrReturned = YES; // now its ready for next SOC
630: e3a02001 mov r2, #1 ; 0x1
634: e59f3018 ldr r3, [pc, #24] ; 654 <.text+0x654>
638: e5c32000 strb r2, [r3]
*******************************************************************************/
inline void EIC_IRQChannelConfig(IRQChannel_TypeDef IRQChannel, FunctionalState NewState)
{
if (NewState==ENABLE) EIC->IER |= 0x0001 << IRQChannel;
else EIC->IER &= ~(0x0001 << IRQChannel);
63c: e2422106 sub r2, r2, #-2147483647 ; 0x80000001
640: e1a02a42 mov r2, r2, asr #20
644: e5923020 ldr r3, [r2, #32]
648: e3c33601 bic r3, r3, #1048576 ; 0x100000
64c: e5823020 str r3, [r2, #32]
650: e8bd8070 ldmia sp!, {r4, r5, r6, pc}
...

00000660 :

// disable this timer2
EIC_IRQChannelConfig( T2TIMI_IRQChannel, DISABLE );

}

}

// ------------ Listing Code start -----------------------------------------