Topic : ARM STR91 with Ride 7 and RLink

Forum : ARM

Original Post
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March 18, 2009 - 4:53pm
Guest

Hi,

I am using Ride 7.16.0000 with ARM-Kit 1.16.0930 and an RLink dngSR7P00000016 on a target board with a STR911FA MX44X6.

I am using the testR7 project from ARM/test, with the CPU set to STR911FM44

Connecting to the target seem OK, and I can read the IdCodes. However, when I try to debug, nothing works:
The program does not seem to stop at the breakpoint and "Pause" and "Reset" give the error "OPI Driver Unable to stop the target. Core does not acknowledge"

What I am doing wrong?

Thanks in advance for your help, Wim Ton
Replies
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March 18, 2009 - 5:45pm
Raisonance Support Team

Hi,

This error could be related to the CPU clock: We don't need a clock for programming, as in this stage it uses the JTAG clock from RLink. But for debugging we need the CPU to receive a clock that is stable and fast enough.
Can you check with a scope that the STR9 receives a stable clock from something on the board?
What is the frequency of this clock?
Note that if the CPU clock is slow, then you have to slow the JTAG clock down. To do that, change the associated setting in the Advanced Debug Options window. See the Getting Started ARM document for more information on this. (try the minimum value of 400)

This error could also come from a connection problem on RST and/or TRST. Can you please confirm that these signals are both connected from the RLink to the STR9, that they are NOT connected to each other, and that no other component prevents the RLink from pulling them down when it needs to.

This error could also come from interference from another device in the JTAG chain. Are there any?

Finally, we should make sure that the programming works fine. Please compile the project in Flash mode, and then with RFlasher or STR9_pgm, try to program it to the Flash and then verify by a Read or Verify command, or simply executing, if there are LEDs on your board...

Best Regards,

Vincent
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March 19, 2009 - 1:25pm
Guest

Hi Vincent,

Thanks for the answer, I had swapped RST and TRST (doh!) I have an external clock of 12 MHz and no other devices in the JTAG chain.

The next hurdle is, that the security bit stays set although a "Erase Full Chip now!" completes without error message.

Best regards, Wim Ton