Hi Lokesh,

We will soon have some new features in Ride7-ARM that will permit direct count of the CPU cycles.

Meanwhile, here is a neat trick: You can use the Cortex-M3's internal cycles counter. You just need to set a bit to enable it, then you can read the number of executed cycles directly as a 32-bit word.

Here is a code sample that does it:

volatile unsigned long ctr = 0;  /* This is the cycles counter */
int main( void )
{
/* Define the cycle counter registers */
#define CYCLESCNT       (*(volatile unsigned long*)0xE0001004)
#define DWTCR           (*(volatile unsigned long*)0xE0001000)
#define DWTCR_CYCCNTENA 0x00000001

    /* Cycles counter enable: Set bit 0 of DWT Control Register */
    DWTCR |= DWTCR_CYCCNTENA;

    ...

    /* Read the cycles counter */
    ctr = CYCLESCNT;

    ...
}

This is a quick and dirty piece of code. It may be very helpful, however we give absolutely no guarantee that it will be fully functional, and you really should think twice when activating this feature in your project.

Other nice features of this counter are that:
- It is read-write, so you can imagine reading the value upon entry of an ISR, and write it back at the end of the ISR, so that the ISR cycles are not accounted.
- It is initialized to 0, so you can just read the counter value at the end of an execution, and it will give a good measure of the application execution time (useful for benchmarking).

Best Regards,