Forum : ARM
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November 26, 2010 - 3:27pm
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Hello Target : STM32F107VCT6 (Cortex M3) Here is the code snippet thread_switch_context: save: Thanks In Advance |
Forum : ARM
| Post Information | Post |
|---|---|
|
November 26, 2010 - 3:27pm
|
Hello Target : STM32F107VCT6 (Cortex M3) Here is the code snippet thread_switch_context: save: Thanks In Advance |
Reason: UsageFault at ldmfd sp!,{r15};
No problem with bx lr .
Cause:
The PC can be specified as the destination register of an LDR instruction.
The loaded value is treated as an address, and the effect of execution is a branch to that address. bit [0] of the loaded value selects the execution state after the branch and must have the value 1.
So whenever you do LDR PC,[]; the loaded value must be (destination_address + 1).
In the debugging environment you will see the last nibble of APSR will change to 3.
but it will change one instruction after ldmfd sp!,{r15};.Thus since bx lr is in pipe its shown as if its
getting excecuted actually the core is jumping to ISR.
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I still have some doubts:
1. Why does it work in the simulator.
2. Why does it show APSR changing and not EPSR and xPSR in the debugging mode.